(1) Field of the Invention
The present invention relates to the fabrication methods used to produce semiconductor devices, and more specifically to methods used to produce interconnect metallization structures.
(2) Description of Prior Art
The semiconductor industry is continually striving to produce higher performing silicon devices, while also attempting to reduce the cost of fabricating these higher performing devices. The ability to fabricate silicon chips, with sub-micron features, has allowed the performance and cost objectives, in part, to be realized. The trend to micro-miniaturization, or the use of smaller silicon device features, has resulted in significant decreases in performance degrading resistances and capacitances, thus allowing faster silicon chips to be produced. In addition the use of sub-micron features allows a greater amount of smaller silicon chips to be obtained from a specific size starting substrate, thus ultimately reducing the manufacturing cost of the chip. Micro-miniaturazation has been accomplished by advances in many semiconductor fabrication disciplines, including photolithography and reactive ion etching, (RIE). The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be routinely produced in photoresist materials. In addition similar advances in dry etching apparatus and procedures have allowed the sub-micron images in photoresist, to be successfully transferred to underlying materials used for the fabrication of silicon chips.
However the use of silicon devices, with sub-micron features, can result in yield and reliability problems, not encountered with counterparts fabricated using less aggressive dimensions. For example in order to increase silicon device density, contact holes, used to connect an overlying interconnect metallization layer to an underlying device region, are fabricated with widths or diameters smaller then 0.5 um. The sub-micron, contact hole openings make it difficult to use aluminum based metallizations as a contact hole fill material. First it is difficult to chemically vapor deposit aluminum, and the use of sputtered aluminum deposition does not result in the desired conformality needed to adequately fill the contact hole with sub-micron openings. In addition the increased current densities encountered with aluminum filled, sub-micron contact holes, could present reliability problems in terms of electromigration. Therefore the industry has used low pressure chemical vapor deposited, (LPCVD), tungsten, as a fill material for narrow diameter contact holes. The more conformal LPCVD process, and the ability of tungsten to withstand high current densities, has made tungsten the material most used, by the semiconductor industry, when filling contact holes with narrow openings.
The formation of tungsten filled contact holes, used to connect underlying active device regions, in a semiconductor substrate, to an overlying interconnect metallization structure, is usually accomplished by initially depositing LPCVD tungsten, followed by removal of the unwanted tungsten, from regions outside the contact hole. The LPCVD deposition can result in a seam in the tungsten fill, or tungsten plug, in the small diameter contact hole. The seam is a result of an LPCVD process which fills the contact hole by deposition on the sides of the hole. The convergence of the tungsten layers, leads to a seam in the center of the tungsten plug. The removal of the unwanted tungsten is, in turn, usually accomplished by selective, reactive ion etching, (RIE), procedures. Selectivity is needed to prevent underlying materials, tiatnium and titanium nitride in this case, from being etched at the completion of the tungsten removal cycle. The desired selectivity is achieved using a halogen containing compound for the RIE processing of tungsten. For example, SF.sub.6, or a Cl.sub.2 containing etchant, results in a large removal rate for tungsten layers, while not significantly attacking the underlying titanium and titanium nitride layers, at the conclusion of the tungsten etch cycle. The extensive RIE processing can result in larger opening in the crevice, in the tungsten fill, to be exposed, greater in width then the opening in the crevice, at the top of the tungsten fill. The larger crevice in the tungsten plug does not allow adequate coverage of overlying interconnect metallizations, and overlying anti-reflective coatings, (ARC), to occur in regions where these layers, usually aluminum and titanium nitride, overlie the crevice in the tungsten plug. If the ARC layer is too thin, or missing in specific regions, aluminum interconnect metallization can be attacked, or eroded in these areas, by a corrosion mechanism. The cavity created by the inability of aluminum to adequately cover the crevice in the tungsten plug, can be a reservoir for moisture, introduced from surrounding non-dense interlevel dielectric layers. The moisture-rich cavity, in turn, can trap halogens, basically chlorine found in the atmosphere, and the combination of moisture and chlorine can result in attack, or corrosion, of aluminum, exposed due to the absence of a protective ARC layer.
Several methods for forming tungsten plugs have been disclosed, such as Ito, et al, in U.S. Pat. No. 5,422,310, Fiordalice, in U.S. Pat. No. 5,420,072, and Marangon, et al. in U.S. Pat. No. 5,407,861. However these inventions do not address the embedded halogens encountered at end point of the etch back process, and the subsequent aluminum corrosion mechanism. This invention will teach a process in which the attack of aluminum, in a cavity created by the underlying tungsten plug definition, is prevented by an anneal step performed in a nitrogen ambient. This anneal process, performed after the tungsten plug etch back procedure, allows a nitrogen containing tungsten layer, to form on the exposed surface of the tungsten crevice, filling the crevice and thus allowing for better coverage of the overlying aluminum and ARC layers to occur. The anneal also allows moisture from the non-dense interlevel dielectric layer, to be removed.